16. USB

16.USB Controller

16.1 Introduction to USB Controller

The CH559 has a built-in USB controller and dual USB transceivers. The features are as follows:

  1. Supports USB Host and USB Device functions
  2. Supports USB 2.0 full speed 12Mbps or low speed 1.5Mbps
  3. Support USB control transfers, bulk transfers, interrupt transfers, iso transfers
  4. Provide dual-port Root-HUB in USB host mode, can manage two USB devices at the same time
  5. Support data packets up to 64 bytes, built-in FIFO, support interrupts and DMA

The USB related registers of the CH559 are divided into 3 groups, and some of the registers are multiplexed between host and device mode.

  1. USB global register
  2. USB device controller register
  3. USB host controller register

16.2 Global Register

Table 16.2.1 USB Global Register
NameAddressDescriptionReset Value
USB_RX_LEND1hUSB Receive Length Register (RO) 0xxx xxxxb
USB_INT_FGD8hUSB Interrupt Flag Register 0010 0000b
USB_INT_STD9hUSB Interrupt Status Register (RO) 00xx xxxxb
USB_MIS_STDAhUSB Miscellaneous Status Register (RO) xx10 1000b
USB_INT_ENE1hUSB interrupt enable register0000 0000b
USB_CTRL E2hUSB control register0000 0110b
USB_DEV_ADE3hUSB device address register0000 0000b
USB_DMA_AHE7hDMA current buffer address high byte (RO) 000x xxxxb
USB_DMA_ALE6hDMA Low byte of current buffer address (RO) xxxx xxx0b
USB_DMA E6hUSB_DMA_AL and USB_DMA_AH form a sfr16 xxxxh

USB Receive Length Register (USB_RX_LEN):

BitNameAccessDescriptionReset value
[7:0]bUSB_RX_LENROnumber of bytes received by the current USB endpoint xxh

USB Interrupt Flag Register (USB_INT_FG bit addressable):

Bit Name Access Description Reset value
7U_IS_NAKROUSB Device mode:
a 1 indicates that a NAK response was received during the current USB transfer; a 0 indicates that a non-NAK response was received
0
6U_TOG_OKROThe current USB transfer DATA0/1 toggle flag match status. If set to is 1 the toggle is as expected and the data are valid. If this bit is 0 data are out of sync, data may be invalid.0
5U_SIE_FREEROIdle status bit of the USB protocol processor. This bit is 0 to indicate busy and USB transfer is in progress. This bit is 1 to indicate USB idle.1
4UIF_FIFO_OVRWUSB FIFO overflow interrupt flag bit. A 1 in this bit indicates a FIFO overflow has occured. Automatically cleared by direct bit access or writing 1 to the register 0
3UIF_HST_SOFRWUSB Host mode:
SOF timer interrupt flag bit. This bit is 1 to indicate a SOF interrupt. This interrupt is triggered by the completion of a SOF packet transfer. Automatically cleared by direct bit access or writing 1 to the register
0
2UIF_SUSPENDRWUSB bus suspend or wake event interrupt flag bit. This bit is 1 to indicate an interrupt. This interrupt is triggered by a USB suspend or wake event. Automatically cleared by direct bit access or writing 1 to the register 0
1UIF_TRANSFERRWUSB transfer complete interrupt flag bit. This bit is 1 to indicate that there is an interrupt. The interrupt is reset by 0. A USB transfer completion trigger. Automatically cleared by direct bit access or writing 1 to the register 0
0UIF_DETECT
UIF_BUS_RST
RW USB Host mode:
set to 1 by hardware when a connection change is detectet, automatically cleared by direct bit access or writing 1 to the register.
USB Device mode:
set to 1 by hardware when a USB device reset is recieved, automatically cleared by direct bit access or writing 1 to the register.
0

USB Interrupt Status Register(USB_INT_ST):

Bit Name Access Description Reset value
7bUIS_IS_NAKROUSB Device mode:
this bit is 1 to indicate that a NAK busy response was received during the current USB transfer. Same as U_IS_NAK
0
6bUIS_TOG_OKROThe current USB transfer DATA0 / 1 synchronization flag match status. This bit is 1 to indicate synchronization; this bit to 0 indicates not to synchronize. Same as U_TOG_OK 0
[5:4]bUIS_TOKENROTransaction PID:
  • 00: indicates an OUT packet;
  • 01: indicates a SOF packet;
  • 10: indicates an IN packet;
  • 11: indicates a SETUP packet.
  • xxb
    [3:0]MASK_UIS_ENDP
    MASK_UIS_H_RES
    RO USB Device mode:
    indicates the endpoint number of the current USB transfer 0000b=EP0 1111=EP15
    USB HOST mode:
    PID ID of of the current USB transfer 0000b=no reponse or timeout other values represend the response PID
    xxxxb

    USB Miscellaneous Status Register (USB_MIS_ST):

    Bit Name Access Description Reset value
    7bUMS_SOF_PRESROUSB Host mode:
    The SOF packet indicates the status bit. This bit is 1 to indicate that a SOF packet will be sent. At this time, any other USB data packets will be automatically postponed.
    x
    6bUMS_SOF_ACT ROUSB Host mode:
    SOF packet transfer status, this bit is 1 to indicate that a SOF packet is being sent; this bit to 0 indicates that the transmission is complete or idle
    x
    5bUMS_SIE_FREEROIdle status bit of the USB protocol processor. This bit is 0 to indicate busy and USB transmission is in progress. This bit is 1 to indicate that USB is idle. Same as U_SIE_FREE 1
    4bUMS_R_FIFO_RDYROUSB receive FIFO data ready status bit, this bit is 0 means the receive FIFO is empty; this bit is 1 means the receive FIFO is not empty 0
    3bUMS_BUS_RESETROUSB bus reset status bit, this bit is 0 means there is no USB bus reset at present; this bit is 1 means the USB bus is currently reset 1
    2bUMS_SUSPENDROUSB suspend status bit, this bit is 0 to indicate that there is currently USB activity; this bit is 1 to indicate that there has been no USB activity for a period of time, requesting suspension 0
    1bUMS_H1_ATTACHROUSB host mode:
    the USB device connection status bit of the HUB1 port. A 1 in this bit indicates that the USB device is connected to HUB1.
    0
    0bUMS_H0_ATTACHROUSB host mode:
    the USB device connection status bit of the HUB0 port. This bit is 1 to indicate that the HUB0 is connected to a USB device.
    0

    USB interrupt enable register (USB_INT_EN):

    Bit Name Access Description Reset value
    7bUIE_DEV_SOFRWUSB Host mode:
    This bit is 1 to enable USB device mode to receive SOF packet interrupt; 0 is disabled
    0
    6bUIE_DEV_NAKRWUSB Device mode:
    This bit is 1 to enable to receive NAK interrupt; 0 is disabled
    0
    5ReservedROreserved 0
    4bUIE_FIFO_OVRWThis bit is 1 to enable FIFO overflow interrupt; this bit is 0 to disable0
    3bUIE_HST_SOFRWThis bit is 1 to enable USB host mode SOF timer interrupt; 0 is disabled0
    2bUIE_SUSPENDRWThis bit is 1 Enable the USB bus suspend or wake event interrupt; 0 disables0
    1bUIE_TRANSFERRWThis bit is 1 to enable the USB transfer completion interrupt; this bit is 0 to disable0
    0bUIE_DETECT
    bUIE_BUS_RST
    RW USB Host Mode:
    Set to 1 to enable USB device connect or disconnect event interrupt. If set to 0 no interrupts on status changes will be generated
    USB Device Mode:
    Set to 1 to enable USB Reset event interrupt. If set to 0 no interrupts on USB Reset events will be generated
    0

    USB Control Register (USB_CTRL):

    BitName Access Description Reset value
    7bUC_HOST_MODERWUSB working mode selection bit, this bit is 0 to select USB device mode (DEVICE); this bit is 1 to select USB host mode (HOST)0
    6bUC_LOW_SPEEDRWUSB bus signal transmission rate selection bit, this bit is 0 to select full speed 12Mbps; this bit is 1 to select low speed 1.5Mbps0
    5bUC_DEV_PU_ENRWUSB device enable and internal pull-up resistor control bit in USB device mode. This bit is 1 to enable USB device transmission and enable internal pull-up resistor0
    [5:4]bUC_SYS_CTRLRW Devicemode:(bUC_HOST_MODE=0)
  • 00b: Disable USB device function, no pull-up resistor
  • 01b: Enable USB device function, no pull-up resitor use external pull-up
  • 10b: Enable USB device function, internal pull-up on
  • 11b: Enable USB device function, internal pull-up weak
  • Hostmode:(bUC_HOST_MODE=1)
  • 00b: normal working state
  • 01b: force DP/DM to output SE0 state
  • 10b: force DP/DM to output J state
  • 11b: force DP/DM to output K state/wake up
  • 00b
    3bUC_INT_BUSY RWUSB transfer completion interrupt flag is automatically suspended before the interrupt flag is not cleared. If this bit is 1, it is automatically suspended before the interrupt flag UIF_TRANSFER is not cleared. It will automatically answer the busy NAK for the device mode, and automatically suspend the subsequent transmission for the host mode; Bit 0 does not pause0
    2bUC_RESET_SIERWUSB protocol processor software reset control bit. When this bit is 1, the USB protocol processor is reset forcibly. It needs to be cleared by software.1
    1bUC_CLR_ALL RWThis bit is 1 to clear the USB interrupt flag and FIFO, which needs to be cleared by software1
    0bUC_DMA_EN RWThis bit is 1 to enable the USB DMA and DMA interrupts; 0 to disable the enable0

    USB device address register (USB_DEV_AD):

    BitName AccessDescriptionReset value
    7bUDA_GP_BITRWUSB general-purpose flag bit: user-defined, can be cleared or set by software0
    [6:0]MASK_USB_ADDRRWIn the host mode, it is the address of the currently operating USB device; in the device mode, it is the address of the USB device00h

    16.3 Device Registers In USB device mode

    The CH559 provides five groups of two-way endpoints 0, 1, 2, 3, and 4. The maximum packet size for each endpoint is 64 bytes. Endpoint 0 is the default endpoint used for control (SETUP) tranfers, sending and receiving uses the same 64-byte data buffer.
    Endpoint 1, Endpoint 2, Endpoint 3 each includes a sending endpoint IN and a receiving endpoint OUT. Each Endpoint can have its own independent 64-byte buffer or double 64-byte data buffer, which supports control, bulk, interrupt and iso transfers. Endpoint 4 is a bit different since it has no own DMA control but shares DMA and with Endpoint 0. It supports control, bulk, interrupt and iso transfers.

    Each pair of endpoints has its own control register UEPn_CTRL and its own transfer size register UEPn_T_LEN (n = 0/1/2/3/4), which is used to set the toggle bit of the endpoint in response to OUT transaction, IN transaction and the sending data Length, etc.
    The pull-up resistor of the USB bus, as necessary for a USB device, can be set by software at any time. When bUC_DEV_PU_EN is set in the USB control register USB_CTRL, the CH559 internally connects a 1k5 pullup to the DP pin or DM pin according to the settings of bUD_LOW_SPEED and thus enable the USB device function as low or full speed device.

    In case of any USB event such as USB bus reset, USB bus suspend, wake-up, USB Setup or USB transfer event, the USB protocol processor will set the corresponding interrupt flag and generates an interrupt request. The application has to query the interrupt flag register USB_INT_FG to determine the event, or if USB interrupt mode is used take the neccessary actions in an USB interrupt service routine.

    There are 3 major events which should be handled by the firmware:

    • UIF_BUS_RST: issued by the host to reset the usb device
    • UIF_SUSPEND: issued by the host to put the usb device into sleep mode
    • UIF_TRANSFER: data transfers to the verious endpoints

    For UIF_TRANSFER the USB interrupt status register USB_INT_ST provides information about type of transfer in the bUIS_TOKEN field and endpoint number in the MASK_UIS_ENDP field. Both fields have to be evaluated to perform the next action on the bus. If the toggle bit bUEP_R_TOG of the OUT transaction for the endpoint is set in advance, U_TOG_OK or bUIS_TOG_OK can be used to check whether toggle bit of the actual received data packet matches the expected toogle bit of the endpoint. If the bit is set data packe is valid. If not the data the data should be discarded.

    Each time the USB send or receive interrupt is processed, the toggle bit of the corresponding endpoint should be modified correctly to synchronize the next data packet sent and check whether the next received data packet is synchronized. In addition, by setting bUEP_AUTO_TOG, the toggle bit will change automatically after each successful transmission or successful reception. The data to be sent by each endpoint is in its own buffer, and the size of the data to be sent is independently set in UEPn_T_LEN. The data received by each endpoint is in its own buffer, but the length of the received data is all in the USB receive length Register USB_RX_LEN, which can be distinguished according to the current endpoint number when USB receive interrupt

    Table 16.3.1 USB Device Related Register List
    NameAddressDescriptionReset Value
    UEP1_CTRL D2hEndpoint 1 Control Register0000 0000b
    UEP1_T_LEND3hEndpoint 1 Send Length Register 0xxx xxxxb
    UEP2_CTRLD4hEndpoint 2 Control Register 0000 0000b
    UEP2_T_LEND5hEndpoint 2 Send Length Register0000 0000b
    UEP3_CTRLD6hEndpoint 3 control register0000 0000b
    UEP3_T_LEND7hEndpoint 3 Send Length Register0xxx xxxxb
    UEP0_CTRLDChEndpoint 0 Control Register0000 0000b
    UEP0_T_LENDDhEndpoint 0 Send Length Register0xxx xxxxb
    UEP4_CTRLDEhEndpoint 4 Control Register0000 0000b
    UEP4_T_LENDFhEndpoint 4 Send Length Register0xxx xxxxb
    UDEVCTRLE4hDevice Control Register0100 x000b
    UEP4_1_MOD2446hEndpoint 1, 4 mode control register0000 0000b
    UEP2_3_MOD2447hEndpoint 2, 3 mode control register0000 0000b
    UEP0_DMA_H2448hEndpoint 0/4 DMA buffer start high byte000x xxxxb
    UEP0_DMA_L2449hEndpoint 0/4 DMA buffer start low Bytexxxx xxx0b
    UEP1_DMA_H244AhEndpoint 1 DMA start high Byte000x xxxxb
    UEP1_DMA_L244BhEndpoint 1 DMA start low Bytexxxx xxxxb
    UEP2_DMA_H244ChEndpoint 2 buffer start address high byte000x xxxxb
    UEP2_DMA_L244DhEndpoint 2 buffer start address low bytexxxx xxx0b
    UEP3_DMA_H244EhEndpoint 3 Buffer Start Address High Byte000x xxxxb
    UEP3_DMA_L244FhEndpoint 3 Buffer Start Address Low Bytexxxx xxx0b
    pUEP*254*hafter bXIR_XSFR is set, this names can be used to address the above xSFR as pdata, which is faster than xdata type addressing

    Endpoint n Control Register (UEPn_CTRL):

    BitName Access Description Reset value
    7bUEP_R_TOGRWSynchronous trigger bit expected by the receiver of USB endpoint n (handling SETUP / OUT transactions). This bit is 0 for DATA0; 1 for DATA10
    6bUEP_T_TOGRWSynchronous trigger bit prepared by the USB endpoint n's transmitter (processing IN transaction). This bit is 0 to send DATA0; 1 to send DATA10
    5ReservedROReserved0
    [3:2]bUEP_R_RESRW Handshake for a SETUP or OUT ransfers:
  • 00: send a ACK handshake to the host(ready)
  • 01: send nothing timeout to the host(used on iso transfers)
  • 10: send a NAK handshake to the host(busy)
  • 11: send a STALL handshake to the host(error)
  • 00b
    [1:0]bUEP_T_RESRW Handshake recieved for IN Transfers:
  • 00: recived a ACK handshake from the host(ready)
  • 01: recived no handshake from the host(timeout or iso)
  • 10: recived a NAK handshake from the host(busy)
  • 11: recived a STALL handshake from the host(error)
  • 00b

    Endpoint n Transmit Length Register (UEPn_T_LEN):

    BitName Access Description Reset value
    [7:0]bUEPn_T_LEN
    bUEP2_T_LEN
    RWSet the number of data bytes to be sent by USB endpoint n (n = 0/1/3/4)
    bUEP2_T_LEN Set the number of data bytes to be sent by USB endpoint 2
    xxh
    00h

    USB Device Physical Port Control Register (UDEV_CTRL):

    BitName Access Description Reset value
    7ROReserved0
    6bUD_RECV_DISRWUSB device physical port receiver disable bit, this bit is 1 to disable the receiver and there is no static power; this bit is 0 to enable the receiver and generate static power1
    5bUD_DP_PD_DISRWUSB device port DP pin internal pull-down resistor disable bit, this bit is 1 to disable internal pull-down resistor; this bit is 0 to enable DP internal pull-down resistor0
    4bUD_DM_PD_DISRWUSB device port DM pin internal pull-down resistor disable bit, this bit is 1 to disable internal pull-down resistor; this bit is 0 to enable DM internal pull-down resistor0
    3bUD_DIFF_IN R0Current differential input status between DP and DM pinsx
    2bUD_LOW_SPEEDRWUSB device physical port low speed mode enable bit, this bit is 1 to select 1.5Mbps low speed mode; this bit is 0 to select 12Mbps full speed mode0
    1bUD_GP_BITRWUSB device mode general flag: user can define it by himself, it can be cleared or set by software0
    0bUD_PORT_ENRWUSB device physical port enable bit, this bit is 1 to enable the physical port; this bit is 0 to disable the physical port0

    USB endpoint 1, 4 mode control register (UEP4_1_MOD):

    BitName Access Description Reset value
    7bUEP1_RX_ENRWThis bit is 0 to disable endpoint 1 reception; 1 to enable endpoint 1 reception (OUT)0
    6bUEP1_TX_ENRWThis bit is 0 to disable endpoint 1 send; enable endpoint 1 send (IN) for 10
    5reserved ROreserve0
    4bUEP1_BUF_MODRWendpoint 1 data buffer mode control bit0
    3bUEP4_RX_ENROThis bit is 0 to disable endpoint 4 reception; enable 1 to enable endpoint 4 reception (OUT)0
    2bUEP4_TX_ENRWThis bit is 0 to disable endpoint 4 transmission; 1 to enable endpoint 4 transmission (IN)0
    [1:0]ReservedROreserved00b

    The combination of bUEP4_RX_EN and bUEP4_TX_EN controls the data buffering of USB endpoints 0 and 4 Zone mode, refer to the table below.

    Table 16.3.2 Endpoints 0 and 4 buffer mode
    bUEP4_RX_ENbUEP4_TX_ENStructure description: starting from UEP0_DMA from low to high
    00Endpoint 0 single 64-byte transmit and receive shared buffers (IN and OUT)
    10Endpoint 0 single 64 Bytes send and receive common buffer; Endpoint 4 single 64-byte receive buffer (OUT)
    01Endpoint 0 and single send 64-byte shared buffer; Endpoint 4 single 64-byte send buffer (IN)
    11Endpoint 0 single 64-byte transmit and receive buffer; Endpoint 4 single 64-byte receive buffer (OUT); Endpoint 4 single 64-byte send buffer (IN).
    The entire 192 bytes are arranged as follows: UEP0_DMA + 0 Address: Endpoint 0 is shared for sending and receiving; UEP0_DMA + 64 Address: Endpoint 4 is receiving; UEP0_DMA + 128 Address: Endpoint 4 is sending

    USB endpoint 2, 3 mode control register (UEP2_3_MOD):

    BitName Access Description Reset value
    7bUEP3_RX_ENRWThis bit is 0 to disable endpoint 3 reception; 1 to enable endpoint 3 reception (OUT)0
    6bUEP3_TX_ENRWThis bit is 0 to disable endpoint 3 transmission; enable 1 to enable endpoint 3 transmission (IN )0
    5Reserved ROReserved0
    4bUEP3_BUF_MODRWEndpoint 3 Data Buffer Mode Control Bit0
    3bUEP2_RX_ENROThis bit is 0 to disable endpoint 2 reception; 1 to enable endpoint 2 reception (OUT)0
    2bUEP2_TX_ENRWThis bit is 0 to disable Endpoint 2 Send; Enable Endpoint 2 Send (IN) for 10
    1ReservedROReserved0
    0bUEP2_BUF_MODRWEndpoint 2 Data Buffer Mode Control Bit0

    Controlled by bUEPn_RX_EN and bUEPn_TX_EN and bUEPn_BUF_MOD (n = 1/2/3) respectively. For the data buffer mode of USB endpoints 1, 2, and 3, refer to the following table. Among the dual 64-byte buffer modes, the first 64-byte buffer is selected according to bUEP_*_TOG = 0 during USB data transfer, and the last 64-byte buffer is selected according to bUEP_*_TOG = 1 to realize automatic switching.

    Table 16.3.3 Endpoint n buffer mode (n = 1/2/3)
    bUEPn_RX_ENbUEPn_TX_ENbUEPn_BUF_MODStructure description: starting from UEPn_DMA from low to high/th>
    00xThe endpoint is disabled and the UEPn_DMA buffer is not used
    100Single 64-byte receive buffer (OUT)
    101Double 64-byte receive buffer, selected by bUEP_R_TOG
    010Single 64-byte receive buffer (IN)
    011Double 64-byte receive buffer, pass bUEP_T_TOG selection
    110single 64-byte receive buffer; single 64-byte transmit buffer
    111Double 64-byte receive buffer, selected by bUEP_R_TOG; double 64-byte send buffer, selected by bUEP_T_TOG. All 256 bytes are arranged as follows: UEPn_DMA + 0 address: endpoint receives when bUEP_R_TOG = 0; UEPn_DMA + 64 address: endpoint receives when bUEP_R_TOG = 1; UEPn_DMA + 128 address: endpoint sends when bUEP_T_TOG = 0; UEPn_DMA + 192 address: bUEP_T_TOG = 1:00 sent by endpoint

    USB Endpoint n Buffer Start Address (UEPn_DMA) (n = 0/1/2/3):

    BitName Access Description Reset value
    [7:0]UEPn_DMA_HRWEndpoint n buffer start address high byte, only the lower 5 bits are valid, the upper 3 bits are fixed to 0xxh
    [7:0]UEPn_DMA_LRWEndpoint n buffer start address low byte, only the upper 7 bits are valid, the lowest bit is fixed to 0, only even address is supportedxxh
    Note: The length of the buffer to receive data is >= min(maximum packet length that may be received + 2 bytes, 64 bytes)

    16.4 Host Register In USB host mode

    The CH559 provides a set of bidirectional host endpoints, including a sending endpoint OUT and a receiving endpoint IN. The maximum data packet length is 64 bytes. It supports control transfers, bulk transfers, interrupt transfers and iso transfers.
    Every USB transaction initiated by the host endpoint always sets the interrupt flag UIF_TRANSFER automatically after processing is complete. The application program can directly query or analyze and analyze the interrupt flag register USB_INT_FG in the USB interrupt service routine, and perform corresponding processing according to each interrupt flag; and, if UIF_TRANSFER is valid, then it needs to continue to analyze the USB interrupt status register USB_INT_ST. The response PID identifier MASK_UIS_H_RES of the transmission transaction is processed accordingly. If the synchronization trigger bit bUH_R_TOG of the IN transaction of the host receiving endpoint is set in advance, you can use U_TOG_OK or bUIS_TOG_OK determines whether the synchronization trigger bit of the currently received data packet matches the synchronization trigger bit of the host receiving endpoint. If the data is synchronized, the data is valid; if the data is not synchronized, the data should be discarded. Each time the USB send or receive interrupt is processed, the synchronization trigger bit of the corresponding host endpoint should be modified correctly to synchronize the next data packet sent and detect whether the next received data packet is synchronized; in addition, by setting bUEP_AUTO_TOG It can be realized that the corresponding synchronization trigger bit is automatically flipped after sending successfully or receiving successfully.

    The USB host token setting register UH_EP_PID is shared with the the USB endpoint 1 control register in the USB device mode. It is used to set the endpoint number of the target device to be operated and the token PID packet identifier of the USB transfer transaction. The data corresponding to the SETUP token and the OUT token are provided by the host sending endpoint. The data to be sent is in the UH_TX_DMA buffer and the length of the data to be sent is set in UH_TX_LEN; the data corresponding to the IN token is returned by the target device to the host Receiving endpoint, the received data is stored in the UH_RX_DMA buffer, and the length of the received data is stored in USB_RX_LEN.

    Table 16.4.1 USB host related register list
    Name Address Description Reset Value
    UH_SETUP D2hUSB host auxiliary setting register 0000 0000b
    UH_RX_CTRLD4hUSB host receiving endpoint control register 0000 0000b
    UH_EP_PID D5hUSB host token setting register 0000 0000b
    UH_TX_CTRLD6hUSB host sending endpoint control Register 0000 0000b
    UH_TX_LEN D7hUSB host transmit length register 0xxx xxxxb
    USB_HUB_STDBhUSB host HUB port status register (read only)0000 0000b
    UHUB0_CTRLE4hUSB host HUB0 port control register 0100 x000b
    UHUB1_CTRLE5hUSB host HUB1 port control register 1100 x000b
    UH_EP_MOD 2447hEndpoint mode control register 0000 0000b
    UH_RX_DMA_H244ChUSB host receive buffer start address high byte 000x xxxxb
    UH_RX_DMA_L244DhUSB host receive buffer start address low byte xxxx xxx0b
    UH_RX_DMA 244ChUH_RX_DMA_L and UH_RX_DMA_H form a 16-bit SFRxxxxh
    UH_TX_DMA_H244EhUSB host send buffer start address high byte 000x xxxxb
    UH_TX_DMA_L244FhUSB host send buffer start address low byte xxxx xxx0b
    UH_TX_DMA 244EhUH_TX_DMA_L and UH_TX_DMA_H form a 16-bit SFRxxxxh
    pUH_* 254*hAfter bXIR_XSFR is set, this names are used to address the above xSFR as a pdata type, which is faster than xdata type addressing

    USB host auxiliary setup register (UH_SETUP):

    BitName Access Description Reset value
    7bUH_PRE_PID_ENRWLow-speed preamble packet PRE PID enable bit, this bit is 1 to enable the USB host to communicate with the low-speed USB device through an external HUB; 0 to disable the low-speed preamble packet, there must be no HUB between the USB host and the low-speed USB device0
    6bUH_SOF_ENRWAutomatically generate SOF packet enable bit. This bit is 1. The SOF packet is automatically generated by the USB host; 0 is not generated automatically, but it can be generated manually.0
    [5:0]ReservedROreserved00h

    USB Host Receive Endpoint Control Register (UH_RX_CTRL):

    BitName Access Description Reset value
    7bUH_R_TOGRWThe expected synchronization trigger bit for the USB host receiver (handling IN transactions). This bit is 0 for DATA0 and 1 for DATA1.0
    [6:5]ReservedROreserved00b
    4bUH_R_AUTO_TOGRWAutomatically flip bUH_R_TOG control bit. This bit is 1 to automatically flip the bUH_R_TOG flag after the USB host receives successfully; 0 to not flip automatically, but can be manually switched.0
    3ReservedROreserved0
    2bUH_R_RESRWUSB host receiver response control bit for IN transaction, 0 means ACK or ready; 1 means no response, used for real-time / synchronous transfer with non-endpoint 0 of the target device0
    [1:0]ReservedROreserved00b

    USB host token setting register (UH_EP_PID):

    BitName Access Description Reset value
    [7:4]MASK_UH_TOKENRWSet the token PID packet ID of this USB transfer transaction0000b
    [3:0]MASK_UH_ENDP RWSet the target to be operated this time Device endpoint number0000b

    USB Host Send Endpoint Control Register (UH_TX_CTRL):

    BitName Access Description Reset value
    7Reserved ROReserved0
    6bUH_T_TOGRWSynchronous trigger bit prepared by the USB host transmitter (handling SETUP / OUT transactions). This bit is 0 to send DATA0; 1 to send DATA10
    5ReservedROReserved0
    4bUH_T_AUTO_TOGRWAutomatically flip bUH_T_TOG control bit, this bit is 1 to automatically flip the bUH_T_TOG flag after the USB host sends successfully; 0 to not flip automatically, but can be manually switched0
    [3:1]ReservedROreserved000b
    0bUH_T_RESRWUSB host transmitter response control bit for SETUP / OUT transaction, 0 means to expect ACK or ready; 1 means no response, used for real-time / synchronous transmission with non-endpoint 0 of the target device0

    USB Host Send Length Register (UH_TX_LEN):

    BitName Access Description Reset value
    [7:0]UH_TX_LENRWSets the number of data bytes to be sent by the USB host send endpointxxh

    USB host HUB port status register (USB_HUB_ST):

    BitName Access Description Reset value
    7bUHS_H1_ATTACHROThe USB device connection status bit of the HUB1 port. A 1 in this bit indicates that a USB device is connected to HUB1; a 0 in this bit indicates no. Same as bUMS_H1_ATTACH0
    6bUHS_HM_LEVEL RORecord the state of the HM pin when the USB device is just connected to the HUB1 port. 0 means low level; 1 means high level. Used to determine full speed or low speed0
    5bUHS_HP_PIN ROCurrent HP pin status, 0 for low level; 1 for high level0
    4bUHS_HM_PIN ROCurrent HM pin status, 0 for low level; 1 for high level0
    3bUHS_H0_ATTACHROThe USB device connection status bit of the HUB0 port. A 1 in this bit indicates that a USB device is connected to HUB0; a 0 in this bit indicates no. Same as bUMS_H0_ATTACH0
    2bUHS_DM_LEVEL RORecord the state of the DM pin when the USB device is just connected to the HUB0 port. 0 means low level; 1 means high level. Used to determine full speed or low speed0
    1bUHS_DP_PIN ROCurrent DP pin status, 0 for low level; 1 for high level0
    0bUHS_DM_PIN ROCurrent DM pin status, 0 for low level; 1 for high level0

    USB host HUBn port control register (UHUBn_CTRL) (n = 0, 1):

    BitName Access Description Reset value
    7bUH1_DISABLE RWFor UHUB1_CTRL is the USB host HUB1 port pin disable bit, this bit is 1 to disable the HP / HM pin, releasing P5.5 / P5.4 will be used for other functions; this bit is 0 to enable P5.5 / P5.4 Used as HP / HM for HUB1 port1
    6bUH_RECV_DIS RWUSB host HUBn port receiver disable bit, this bit is 1 to disable the receiver and there is no static power consumption; this bit is 0 to enable the receiver and generate static power consumption1
    5bUH_DP_PD_DISRWUSB host HUBn port DP / HP pin internal pull-down resistor disable bit, this bit is 1 to disable internal pull-down resistor; this bit is 0 to enable internal pull-down resistor0
    4bUH_DM_PD_DISRWUSB host HUBn port DM / HM pin internal pull-down resistor disable bit, this bit is 1 to disable internal pull-down resistor; this bit is 0 to enable internal pull-down resistor0
    3bUH_DIFF_IN R0For UHUB0_CTRL is the current differential input state between the DP and DM pins For UHUB1_CTRL is the current differential input state between the HP and HM pinsx
    2bUH_LOW_SPEEDRWUSB host HUBn port low speed mode enable bit, this bit is 1 to select 1.5Mbps low speed mode; this bit is 0 to select 12Mbps full speed mode0
    1bUH_BUS_RESETRWUSB host HUBn port bus reset control bit, this bit is 1 to force the HUBn port to output USB bus reset; this bit is 0 to end the output0
    0bUH_PORT_EN RWUSB host HUBn port enable bit, this bit is 0 to disable the HUBn port; this bit is 1 to enable the HUBn port. This bit is automatically cleared when the USB device is disconnected0

    USB Host Endpoint Mode Control Register (UH_EP_MOD):

    BitName Access Description Reset value
    7ReservedROReserved0
    6bUH_EP_TX_ENRWThis bit is 0 to disable the USB host from sending endpoints to send data; this bit is 1 to enable the USB host to send endpoints to send data (SETUP / OUT)0
    5ReservedROreserved0
    4bUH_EP_TBUF_MODRWUSB host transmit endpoint data buffer mode control bit0
    3bUH_EP_RX_ENROThis bit is 0 to disable the USB host receiving endpoint from receiving data; this bit is 1 to enable the USB host receiving endpoint to receive data (IN)0
    [2:1]ReservedROreserved00b
    0bUH_EP_RBUF_MODRWUSB host receive endpoint data buffer mode control bit0

    Controlled by the combination of bUH_EP_TX_EN and bUH_EP_TBUF_MOD, the USB host sends endpoint data buffer mode, refer to the table below.

    Table 16.4.2 Host transmit buffer mode
    bUH_EP_TX_ENbUH_EP_TBUF_MODStructure description: Start with UH_TX_DMA
    0xEndpoint is disabled, UH_TX_DMA buffer is not used
    10Single 64-byte transmit buffer (SETUP / OUT)
    11Double 64-byte transmit buffer, selected by bUH_T_TOG:
    When bUH_T_TOG = 0, the first 64-byte buffer is selected;
    when bUH_T_TOG = 1, the latter 64-byte buffer is selected

    by the combination of bUH_EP_RX_EN and bUH_EP_RBUF_MOD to control the USB host receiving endpoint data buffer Mode, refer to the table below.

    Table 16.4.3 Host receive buffer mode
    bUH_EP_RX_ENbUH_EP_RBUF_MODStructure description: Start with UH_RX_DMA
    0xEndpoint is disabled, UH_RX_DMA buffer is not used
    10Single 64-byte receive buffer (IN)
    11Double 64-byte receive buffer, selected by bUH_R_TOG:
    When bUH_R_TOG = 0, select the first 64-byte buffer;
    when bUH_R_TOG = 1, select the last 64-byte buffer

    USB Host receive buffer start address (UH_RX_DMA):

    BitName Access Description Reset value
    [7:0]UH_TX_DMA_HRWUSB host send buffer start address high byte, only the lower 5 bits are valid, the upper 3 bits are fixed to 0xxh
    [7:0]UH_TX_DMA_LRWUSB host send buffer start address low byte, only the upper 7 bits are valid, the lowest bit is fixed to 0, only supports even addressxxh

    USB Host transmit start address (UH_TX_DMA):

    BitName Access Description Reset value
    [7:0]UH_TX_DMA_HRWUSB host send buffer start address high byte, only the lower 5 bits are valid, the upper 3 bits are fixed to 0xxh
    [7:0]UH_TX_DMA_LRWUSB host send buffer start address low byte, only the upper 7 bits are valid, the lowest bit is fixed to 0, only supports even addressxxh